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NB4N527S 3.3V, 2.5Gb/s Dual AnyLevelTM to LVDS Receiver/Driver/Buffer/ Translator with Internal Input Termination
NB4N527S is a clock or data Receiver/Driver/Buffer/Translator capable of translating AnyLevelTM input signal (LVPECL, CML, HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the distance, noise immunity of the system design, and transmission line media, this device will receive, drive or translate data or clock signals up to 2.5 Gb/s or 1.5 GHz, respectively. The NB4N527S has a wide input common mode range of GND + 50 mV to VCC - 50 mV combined with two 50 W internal termination resistors is ideal for translating differential or single-ended data or clock signals to 350 mV typical LVDS output levels without use of any additional external components (Figure 6). The device is offered in a small 3 mm x 3 mm QFN-16 package. NB4N527S is targeted for data, wireless and telecom applications as well as high speed logic interface where jitter and package size are main requirements. Application notes, models, and support documentation are available on www.onsemi.com. * Maximum Input Clock Frequency up to 1.5 GHz * Maximum Input Data Rate up to 2.5 Gb/s (Figure 5) * 470 ps Maximum Propagation Delay\ * 1 ps Maximum RMS Jitter * 140 ps Maximum Rise/Fall Times * Single Power Supply; VCC = 3.3 V $10% * Temperature Compensated TIA/EIA-644 Compliant LVDS Outputs * Internal 50 W Termination Resistor per Input Pin * GND + 50 mV to VCC - 50 mV VCMR Range * Pb-Free Packages are Available
http://onsemi.com MARKING DIAGRAM*
16 1
1 QFN-16 MN SUFFIX CASE 485G
NB4N 527S ALYW G G
A L Y W G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
(Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
50 W* VTD0 D0 D0 VTD0 50 W* VTD1 50 W* Q0 Q0
VOLTAGE (130 mV/div)
D1 D1 Device DDJ = 10 ps VTD1 50 W*
Q1 Q1
Figure 1. Functional Block Diagram
*RTIN
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with PRBS 223-1 (VINPP = 400 mV; Input Signal DDJ = 14 ps)
(c) Semiconductor Components Industries, LLC, 2006
1
June, 2006 - Rev. 3
Publication Order Number: NB4N527S/D
NB4N527S
Exposed Pad (EP) VTD0 D0 16 VTD1 D1 D1 VTD1 1 2 NB4N527S 3 4 10 Q1 9 Q1 15 D0 VTD0 14 13 12 Q0 11 Q0
5 GND
6 NC
7 NC
8 VCC
Figure 3. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin 1 2 3 4 5 6, 7 8 9 10 11 12 13 14 15 16 EP Name VTD1 D1 D1 VTD1 GND NC VCC Q1 Q1 Q0 Q0 VTD0 D0 D0 VTD0 LVDS Output LVDS Output LVDS Output LVDS Output - LVPECL, CML, LVDS, LVCMOS, LVTTL, HSTL LVPECL, CML, LVDS, LVCMOS, LVTTL, HSTL - I/O - LVPECL, CML, LVDS, LVCMOS, LVTTL, HSTL LVPECL, CML, LVDS, LVCMOS, LVTTL, HSTL - - Description Internal 50 W termination pin for D1. (RTIN) Noninverted differential clock/data D1 input (Note 1). Inverted differential clock/data D1 input (Note 1). Internal 50 W termination pin for D1. (RTIN) 0 V. Ground. No connect. Positive Supply Voltage. Inverted D1 output. Typically loaded with 100 W receiver termination resistor across differential pair. Noninverted D1 output. Typically loaded with 100 W receiver termination resistor across differential pair. Inverted D0 output. Typically loaded with 100 W receiver termination resistor across differential pair. Noninverted D0 output. Typically loaded with 100 W receiver termination resistor across differential pair. Internal 50 W termination pin for D0. Noninverted differential clock/data D0 input (Note 1). Inverted differential clock/data D0 input (Note 1). Internal 50 W termination pin for D0. Exposed pad. EP on the package bottom is thermally connected to the die improved heat transfer out of package. The pad is not electrically connected to the die, but is recommended to be soldered to GND on the PCB.
1. In the differential configuration when the input termination pins(VTD0/VTD0, VTD1/ VTD1) are connected to a common termination voltage or left open, and if no signal is applied on D0/D0, D1/D1 input, then the device will be susceptible to self-oscillation.
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NB4N527S
Table 2. ATTRIBUTES
Characteristics Moisture Sensitivity (Note 2) Flammability Rating ESD Protection Oxygen Index: 28 to 34 Human Body Model Machine Model Charged Device Model Value Level 1 UL 94 V-0 @ 0.125 in > 2 kV > 200 V > 1 kV 281
Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol VCC VI IIN IOSC Parameter Positive Power Supply Positive Input Input Current Through RT (50 W Resistor) Output Short Circuit Current Line-to-Line (Q to Q) Line-to-End (Q or Q to GND) Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 3) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm 1S2P (Note 3) QFN-16 QFN-16 QFN-16 Condition 1 GND = 0 V GND = 0 V Static Surge Q or Q to GND Q to Q QFN-16 Continuous Continuous VI = VCC Condition 2 Rating 3.8 3.8 35 70 12 24 -40 to +85 -65 to +150 41.6 35.2 4.0 265 265 Unit V V mA mA mA C C C/W C/W C/W C
TA Tstg qJA qJC Tsol
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard multilayer board - 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB4N527S
Table 4. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS VCC = 3.0 V to 3.6 V, GND = 0 V, TA = -40C to +85C
Symbol ICC Power Supply Current (Note 8) Characteristic Min Typ 40 Max 53 Unit mA
DIFFERENTIAL INPUTS DRIVEN SINGLE-ENDED (Figures 11, 12, 16, and 18) Vth VIH VIL Input Threshold Reference Voltage Range (Note 7) Single-ended Input HIGH Voltage Single-ended Input LOW Voltage GND +100 Vth + 100 GND VCC - 100 VCC Vth - 100 mV mV mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7, 8, 9, 10, 17, and 19) VIHD VILD VCMR VID RTIN Differential Input HIGH Voltage Differential Input LOW Voltage Input Common Mode Range (Differential Configuration) Differential Input Voltage (VIHD - VILD) Internal Input Termination Resistor 100 GND GND + 50 100 40 50 VCC VCC - 100 VCC - 50 VCC 60 mV mV mV mV W
LVDS OUTPUTS (Note 4) VOD DVOD VOS DVOS VOH VOL Differential Output Voltage Change in Magnitude of VOD for Complementary Output States (Note 9) Offset Voltage (Figure 15) Change in Magnitude of VOS for Complementary Output States (Note 9) Output HIGH Voltage (Note 5) Output LOW Voltage (Note 6) 900 250 0 1125 0 1 1425 1075 1 450 25 1375 25 1600 mV mV mV mV mV mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 14. 5. VOHmax = VOSmax + 1/2 VODmax. 6. VOLmax = VOSmin - 1/2 VODmax. 7. Vth is applied to the complementary input when operating in single-ended mode. 8. Input termination pins open, Dx/Dx at the DC level within VCMR and output pins loaded with RL = 100 W across differential. 9. Parameter guaranteed by design verification not tested in production.
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NB4N527S
Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; (Note 10)
-40C Symbol VOUTPP fDATA tPLH, tPHL tSKEW Characteristic Output Voltage Amplitude (@ VINPPmin) fin 1.0 GHz (Figure 4) fin= 1.5 GHz Maximum Operating Data Rate Differential Input to Differential Output Propagation Delay Duty Cycle Skew (Note 11) Within Device Skew (Note 17) Device-to-Device Skew (Note 15) fin = 1.0 GHz fin = 1.5 GHz Deterministic Jitter (Note 14) fDATA = 622 Mb/s fDATA = 1.5 Gb/s fDATA = 2.488 Gb/s Crosstalk Induced Jitter (Note 16) Input Voltage Swing/Sensitivity (Differential Configuration) (Note 12) Output Rise/Fall Times @ 250 MHz (20% - 80%) Q, Q 100 60 100 RMS Random Clock Jitter (Note 13) Min 220 200 1.5 270 Typ 350 300 2.5 370 8 5 30 0.5 0.5 6 7 10 20 470 45 25 100 1 1 20 20 25 40 VCC- GND 140 100 60 100 Max Min 220 200 1.5 270 25C Typ 350 300 2.5 370 8 5 30 0.5 0.5 6 7 10 20 470 45 25 100 1 1 20 20 25 40 VCC- GND 140 100 60 100 Max Min 220 200 1.5 270 85C Typ 350 300 2.5 370 8 5 30 0.5 0.5 6 7 10 20 470 45 25 100 1 1 20 20 25 40 VCC- GND 140 Max Unit mV Gb/s ps ps
tJITTER
ps
VINPP tr tf
mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Measured by forcing VINPPmin with 50% duty cycle clock source and VCC - 1400 mV offset. All loading with an external RL = 100 W across "D" and "D" of the receiver. Input edge rates 150 ps (20%-80%). 11. See Figure 13 differential measurement of tskew = |tPLH - tPHL| for a nominal 50% differential clock input waveform @ 250 MHz. 12. Input voltage swing is a single-ended measurement operating in differential mode. 13. RMS jitter with 50% duty cycle input clock signal. 14. Deterministic jitter with input NRZ data at PRBS 223-1 and K28.5. 15. Skew is measured between outputs under identical transition @ 250 MHz. 16. Crosstalk induced jitter is the additive deterministic jitter to channel one with channel two active both running at 622 Gb/s PRBS 223 -1 as an asynchronous signals. 17. The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition.
400 OUTPUT VOLTAGE AMPLITUDE (mV) 350 300 250 200 150 100 50 0 0 0.5 1 1.5 2 2.5 3 INPUT CLOCK FREQUENCY (GHz) 85C 25C -40C
Figure 4. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fin) and Temperature (@ VCC = 3.3 V)
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NB4N527S
VOLTAGE (63.23 mV/div)
Device DDJ = 10 ps
TIME (58 ps/div)
Figure 5. Typical Output Waveform at 2.488 Gb/s with PRBS 223-1 and OC48 mask (VINPP = 100 mV; Input Signal DDJ = 14 ps)
RC 1.25 kW Dx 50 W VTDx VTDx 50 W Dx 1.25 kW I
RC 1.25 kW
1.25 kW
Figure 6. Input Structure
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NB4N527S
VCC VCC VCC VCC
Zo = 50 W LVPECL Driver VTDx VTDx Zo = 50 W
NB4N527S Dx 50 W* 50 W* Dx LVDS Driver
Zo = 50 W VTDx VTDx Zo = 50 W VTDx = VTDx
NB4N527S Dx 50 W* 50 W* Dx
VTDx = VTDx = VCC - 2.0 V GND GND GND GND
Figure 7. LVPECL Interface
Figure 8. LVDS Interface
VCC
VCC
VCC
VCC
CML Driver
Zo = 50 W VCC VTDx VTDx Zo = 50 W VTDx = VTDx = VCC
NB4N527S Dx 50 W* 50 W* Dx HSTL Driver
Zo = 50 W VTDx VTDx Zo = 50 W
NB4N527S Dx 50 W* 50 W* Dx
GND
GND
GND
VTDx = VTDx = GND or VDD/2 Depending on Driver.
GND
Figure 9. Standard 50 W Load CML Interface
Figure 10. HSTL Interface
VCC
VCC
VCC
VCC
Zo = 50 W LVCMOS Driver VTDx VTDx
NB4N527S Dx 50 W* 50 W* Dx LVTTL Driver
Zo = 50 W VTDx VTDx
NB4N527S Dx 50 W* 50 W* Dx
2.5 kW GND GND VTDx = VTDx = OPEN Dx = GND GND GND
1.5 kW
GND VTDx = OPEN Dx = GND
GND
Figure 11. LVCMOS Interface
*RTIN, Internal Input Termination Resistor.
Figure 12. LVTTL Interface
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NB4N527S
D VINPP = VIH(Dx) - VIL(Dx) D Q VOUTPP = VOH(Qx) - VOL(Qx) Q tPHL tPLH
Figure 13. AC Reference Measurement
LVDS Driver Device
Q
Zo = 50 W 100 W
D
LVDS Receiver Device
Q
Zo = 50 W
D
Figure 14. Typical LVDS Termination for Output Driver and Device Evaluation
QN VOS QN VOD
VOH
VOL
Figure 15. LVDS Output
D VIH Vth VIL D
D D Vth
Figure 16. Differential Input Driven Single-Ended
Figure 17. Differential Inputs Driven Differentially
VCC VCC Vthmax D Vth VIHmin D VILmin VEE VIHmax VILmax VCMR
VIH(MAX) VIL VIH VINPP = VIHD - VILD VIL VIH VIL(MIN)
Vthmin GND
Figure 18. Vth Diagram
Figure 19. VCMR Diagram
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NB4N527S
ORDERING INFORMATION
Device NB4N527SMN NB4N527SMNG NB4N527SMNR2 NB4N527SMNR2G Package QFN-16 QFN-16 (Pb-Free) QFN-16 QFN-16 (Pb-Free) Shipping 123 Units / Rail 123 Units / Rail 3000 / Tape & Reel 3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NB4N527S
PACKAGE DIMENSIONS
16 PIN QFN CASE 485G-01 ISSUE C
D A B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50
PIN 1 LOCATION
0.15 C 0.15 C 0.10 C TOP VIEW
16 X
0.08 C SIDE VIEW A1 C
16X
L
5
NOTE 5 4
16X
K
1 12
16X
0.10 C A B 0.05 C
NOTE 3
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
CCC CCC CCC
(A3) D2 e
8 9 16 13
E
A
SEATING PLANE
DIM A A1 A3 b D D2 E E2 e K L
SOLDERING FOOTPRINT*
3.25 0.128 0.30 0.012
0.575 0.022
EXPOSED PAD
EXPOSED PAD
E2 e
3.25 0.128
1.50 0.059
b BOTTOM VIEW 0.50 0.02
0.30 0.012
SCALE 10:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NB4N527S/D

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